Advances in semiconductor manufacturing technology have resulted in, among other things, reducing the cost of sophisticated electronics to the extent that integrated circuits have become ubiquitous in the modern environment.
As is well-known, integrated circuits are typically manufactured in batches, and these batches usually contain a plurality of semiconductor wafers within and upon which integrated circuits are formed through a variety of semiconductor manufacturing steps, including, for example, depositing, masking, patterning, implanting, etching, planarizing and so on.
Completed wafers are tested to determine which die, or integrated circuits, on the wafer are capable of operating according to predetermined specifications. In this way, integrated circuits that cannot perform as desired are not packaged, or otherwise incorporated into finished products.
It is common to manufacture integrated circuits on roughly circular semiconductor substrates, or wafers. Further, it is common to form such integrated circuits so that conductive regions disposed on, or close to, the uppermost layers of the integrated circuits are available to act as terminals for connection to various electrical elements disposed in, or on, the lower layers of those integrated circuits. In testing, these conductive regions are commonly contacted with a probe card.
Historically, unsingulated integrated circuits on a wafer were tested one at a time. In order to reduce costs and improve return on investment, the amount of time that each wafer spends in the testing process should be reduced. Various methods and apparatus have been sought by manufacturers for testing two or more integrated circuits at the same time. In this way, wafer throughput can be increased. A typical requirement for testing more than one integrated circuit at a time is to increase the number of tester channels on the tester. In such a parallel testing scheme, when a first one of the two or more integrated circuits is determined to fail the test program, the one or more remaining integrated circuits in that group must continue with, and complete, the test sequence before another group of integrated circuits on the wafer can begin the process of being simultaneously tested. This means that the tester channels dedicated to the integrated circuit that failed are not usefully occupied until the test system is ready to test the next group of integrated circuits on the wafer.
What is needed are methods and apparatus for collecting process characterization data in the time period between the detection of a failure of a first one of a group of integrated circuits being simultaneously tested, and prior to the completion of the test sequence for a “good” integrated circuit, to collect electrical data from one or more process characterization test sites that are local to, that is in proximity with, the failed device under test.